1. Field of the Invention
The present invention relates to an output buffer circuit and in particular, to an output buffer which isolates the well of an output pull-up transistor from a power supply utilizing a switching component fabricated from standard CMOS components.
2. Description of the Related Art
FIG. 1 shows a diagram of a conventional CMOS driver circuit 10 conveying signals to bus 12. Driver circuit 10 includes input node 14 receiving a digital input voltage signal of either a logical high value equal to the power supply voltage (V.sub.cc) present on power supply rail 16, or a logical low value equal to ground 18.
Simple driver circuit 10 also includes PMOS pull-up transistor 20 featuring a gate, source, and drain. The gate is in electrical communication with input node 14. The source is in electrical communication with power supply rail 16. PMOS pull up transistor 20 is formed within N-well 22 also in electrical communication with power supply rail 16.
Driver circuit 10 further includes NMOS pull-down transistor 24 featuring a gate, source, and drain. The gate is in electrical communication with input node 14. The source is in electrical communication with ground 18. NMOS pull down transistor 24 is formed within P-type substrate 26 that is also grounded.
The drain of PMOS pull-up transistor 20 and the drain of NMOS pull-down transistor 24 are in electrical communication with each other and with output node 28. Output node 28 is in electrical communication with bus 12.
During operation of driver circuit 10, an input voltage signal is applied to the transistor gates through input node 14. The input voltage signal is either low (ground) or high (power supply voltage). Where the input voltage is equal to the voltage of power supply rail 16, the gate-to-source voltage (V.sub.gs) of PMOS pull-up transistor 20 is zero, and PMOS pull-up transistor 20 is deactivated. At the same time, the V.sub.gs of NMOS pull-down transistor 24 is positive, and transistor 24 is activated. Thus where the input voltage signal is high, the drains of transistors 20 and 24 respectively are pulled to ground, and output node 28 exhibits low voltage.
Conversely, where the input voltage signal is zero, V.sub.gs of PMOS pull-up transistor 20 is negative and transistor 20 is activated. At the same time, V.sub.gs of NMOS pull-down transistor 24 is zero and transistor 24 is deactivated. Thus where the input voltage signal is low, the drains of transistors 20 and 24 respectively are pulled to the power supply voltage, and output node 28 exhibits high voltage. The two states of driver circuit 10 are summarized below in TABLE A:
TABLE A INPUT NODE P.sub.in N.sub.in OUTPUT NODE High Off On Low Low On Off High
Occasionally a need arises for more than one driver circuit to communicate on the same bus. Under these conditions, a driver circuit must be capable of operating in three states, with the driver circuit deactivated in the third state to permit other driver circuit(s) to communicate signals along the bus without interference.
Accordingly, FIG. 2 shows a conventional three-state driver circuit (also known as a high-impedance, or "high-Z", driver circuit). High-Z driver circuit 100 can be configured in a third, high impedance state, wherein a voltage on input node 114 is precluded from affecting a voltage on buffer output node 128.
Specifically, high-Z driver circuit 100 includes an output inverter 129 including PMOS output pull-up transistor 120 and NMOS output pull-down transistor 124. Output inverter 129 corresponds to the simple driver circuit 10 of FIG. 1. PMOS output pull-down transistor 120 is formed in N-well 122. Tri-state driver circuit 100 further includes pre-driver circuit 130 including input inverter 132 and first through fourth enable transistors 142, 144, 146, and 147 respectively.
Input inverter 132 includes PMOS input pull-up transistor 134. The gate of transistor 134 is in electrical communication with input node 114, and the source of transistor 134 is in electrical communication with power supply rail 116.
Input inverter 132 further includes NMOS input pull-down transistor 136. The gate of transistor 136 is in electrical communication with input node 114, and the source of transistor 136 is in electrical communication with ground 118. NMOS input pull-down transistor 136 is formed within P-type substrate 126 which is also grounded.
The drain of PMOS input pull-up transistor 134 and the drain of NMOS input pull-down transistor 136 form first and second conductive paths 138 and 140, respectively. The voltage appearing on conductive paths 138 and 140 is determined by first through fourth enable transistors 142, 144, 146 and 147, respectively.
The gates of first and second enable transistors 142 and 144 are connected to enable input node 148. The gates of third and fourth enable transistors 146 and 147 connected to enable inverse input node 150.
When enable input node 148 is high and enable inverse input node 150 is low, first enable transistor 142 and third enable transistor 146 are activated, and second enable transistor 144 and fourth enable transistor 147 are deactivated. This has the effect of placing the drains of transistors 134 and 136 in electrical communication, such that buffer circuit 130 operates in conjunction with output inverter circuit 129 in essentially the same manner as circuit 10 of FIG. 1. As described above in conjunction with FIG. 1, transistors 120 and 124 of output inverter 129 are then selectively activated/deactivated to convey an output voltage to output node 128 equal to the voltage on input node 114.
Conversely, when enable input 148 is low and enable inverse input 150 is high, driver circuit 100 is placed into a third configuration. In this third configuration, first and third enable transistors 142 and 146 are deactivated, and second and fourth enable transistors 144 and 147 are activated.
This third configuration has the effect of isolating first and second current paths 138 and 140 from one another. Moreover, because second enable transistor 144 is activated, first electrical path 138 between the drain of PMOS input pull-up transistor 134 and the gate PMOS output pull-up transistor 120 is raised to the power supply voltage on power supply rail 116. Because fourth enable transistor 147 is activated, second electrical pathway 140 is lowered to ground. When driver 100 is thus placed into the third state, appearance of a voltage signal at input node 114 will not affect the voltage at buffer output node 128. High-Z driver circuit 100 is thus inactive while second buffer structure 152 communications along bus 112. Operation of the high-Z buffer circuit of FIG. 2 is summarized in TABLE B below:
TABLE B INPUT ENABLE TRANS. TRANS. TRANS. TRANS. TRANS. TRANS. OUTPUT NODE ENABLE INVERSE 134 136 142 & 146 144 & 148 PATH 1 PATH 2 120 124 NODE High High Low Off On On Off Low Low On Off High (GND) (GND) Low High Low On Off On Off High High Off On Low (V.sub.cc) (V.sub.cc) High Low High Off On Off On High Low Off Off Z (V.sub.cc) (GND) Low Low High On Off On Off High Low Off Off Z (V.sub.cc) (GND)
While the high-Z driver circuit described above in FIG. 2 is suitable for some applications, it has a number of serious disadvantages.
One problem with the conventional buffer architecture becomes apparent during power down of the circuit.
Referring back to FIG. 2, in a power down situation the voltage appearing on power supply rail 116 may be at or close to ground, while a voltage is conveyed to input node 114 by an active device. Under such power down conditions, pre-driver circuit 130 may communicate a corresponding input voltage to the gate of NMOS output pull-down transistor 124. Simultaneously, it is possible that second buffer structure 152 could transmit a voltage signal on bus 112, thereby causing this voltage to appear on buffer output node 128. Under the power-down conditions just described, the gate-to-source voltage (V.sub.gs) of output NMOS pull-down transistor 124 would be positive, activating transistor 124 and causing a flow of current from buffer output node 128 into ground. This unwanted current flow can strain transistor 124 and reduce the voltage at output node 128, possibly disrupting communication by second buffer structure 152 along bus 112.
Therefore, there is a need in the art for a buffer structure which prevents unwanted activation of the output pull-down transistor during power down conditions which could create a current path between the buffer output node and ground.
Another problem with the conventional buffer architecture becomes apparent when a high voltage appears at the output node. Specifically, where driver circuit 100 of FIG. 2 is operating on bus 112 with a second buffer structure 152, a voltage may appear on bus 112 (and hence at buffer output node 128 of the driver circuit 100) in excess of the power supply voltage (V.sub.CC). This can occur, for example, when second buffer structure 152 utilizes a power supply voltage greater than V.sub.CC.
Appearance of such an elevated voltage on the buffer output node poses several dangers.
One danger is that the PMOS output pull-up transistor may turn on, enabling current to flow from the drain through the channel to the source. In this manner, voltage limits of the internal transistors of the buffer structure may be exceeded, leading to irreversible device damage and failure.
Therefore, there is a need in the art for a high-Z buffer structure which prevents activation of the output pull-up transistor in the third, high impedance state as could be caused by the appearance of a high voltage on the buffer output node.
A second danger posed by the appearance of a high voltage on the output node is that the P/N junction formed at the interface between the P+drain and the N-well of the output pull-up transistor may become forward-biased. Because the N-well is connected to the power supply rail, forward-biasing the drain-well P/N junction would result in a flow of current into the power supply rail, disrupting and destabilizing the power supply voltage.
This is illustrated in FIGS. 3A-3B, which depict cross-sectional views of PMOS output pull-up transistor 120 of driver circuit 100 of FIG. 2. In FIG. 3A, PMOS output pull-up transistor 120 is operating under normal conditions, wherein the voltage on buffer output node 128 is less than or equal to the voltage on power supply rail 116. Application of a low voltage signal to gate 120a of PMOS output pull-up transistor 120 activates transistor 120, such that current flows from power supply 116 through source 120b to output node 128.
FIG. 3B illustrates abnormal operating conditions, wherein a voltage exceeding that of power supply rail 116 appears on output node 128. PMOS output pull-up transistor 120 is formed within N-well 122, and N-well 122 is tied to source 120a. High voltage on output node 128 may forward-bias the P/N junction between drain 120c of transistor 120 and N-well 122. This forward-biasing may result in current flow from drain 120c through N-well 122 into power supply rail 116, posing a number of serious problems for the buffer structure. These problems include destabilization of the power supply voltage and possible device failure.
Therefore, there is a need in the art for a buffer structure which prevents forward-biasing of the P/N diode at the P+ drain/N-well interface of the output pull-up transistor that can lead to disruption of the power supply voltage.
One approach to solving the above-described problem is proposed in U. S. Pat. No. 5,338,978 to Larsen et al. ("the Larsen Patent"). The general operation of the buffer of the Larsen Patent is depicted in FIG. 4.
Buffer circuit 400 includes output pull-up PMOS transistor PT1 formed in N-well 422. First switch 459 is interposed between buffer output node 428 and the gate of output pull-up PMOS transistor PT1. First switch 459 is activated when the voltage on buffer output node 428 exceeds the power supply voltage V.sub.CC.
Second switch 460 is interposed between N-well 422 and power supply rail 416. Second switch 460 is manipulable to selectively isolate N-well 422 from power supply rail 416 based upon the voltage present on the gate of output pull-up PMOS transistor PT1.
When voltage V.sub.OUT on buffer output node 428 rises above the buffer supply V.sub.CC, first switch 459 is activated. This causes the voltage on the gate of output pull-up transistor PT1 to rise to V.sub.OUT, in turn deactivating second switch 460 and isolating N-well 422 from power supply 416.
While the buffer structure proposed by the Larsen Patent is suitable for some applications, it suffers from a number of important disadvantages.
For example, deactivation of second switch 460 to isolate N-well 422 from power supply 416 is controlled by the voltage on the gate of output pull-up transistor PT1. While the voltage on the gate of output pull-up PT1 changes when V.sub.OUT &gt;V.sub.CC and first switch 459 is activated, the voltage on the gate of output pull-up transistor PT1 also changes with the voltage present on input node 414. Second switch 460 thus receives a constantly-changing input signal regardless of the actual magnitude of V.sub.OUT. Where input node 414 is at the power supply V.sub.CC, second switch 460 is close to deactivation.
Therefore, there is a need in the art for a buffer structure which isolates the well containing the output transistor independent of the voltage present on the buffer input node and only when the voltage on the buffer output node exceeds the buffer power supply.